Abstract

The relentless scaling of semiconductor technology, leading to higher gate densities and lower operating voltages, has introduced a critical bottleneck in manufacturing: excessive power dissipation during scan-based testing. While essential for achieving high fault coverage, conventional Automatic Test Pattern Generation (ATPG) methodologies are power-agnostic. Their primary objective is maximizing fault coverage, often resulting in test patterns that induce unrealistic switching activity, which can cause thermal hotspots, severe IR drop, and ultimately reduce device reliability. These power violations can lead to immediate yield loss or latent, in-field failures. This paper details a comprehensive power-aware ATPG methodology designed to mitigate these risks without compromising test quality. The proposed framework integrates two synergistic techniques: scan chain reordering, which structurally minimizes shift transitions by optimizing the physical order of flip-flops based on their proximity, and intelligent X-filling, which strategically assigns logic values to "don't care" bits to actively prevent unnecessary switching. This approach transforms previously random don't-care bits into a powerful tool for power reduction. The methodology was implemented and validated on a T80 processor core synthesized using a 90nm technology node. Results were benchmarked against a conventional ATPG flow, demonstrating a dramatic reduction in average shift switching activity, which was consistently constrained below 25% compared to erratic peaks over 50% in the baseline. Furthermore, peak capture power remained well within the design's switching budget. This work validates a practical and scalable solution that directly contributes to enhanced manufacturing yield, improved chip reliability, and reduced test costs, making it a fundamental requirement for producing complex modern SoCs.