Abstract

Objective: The objective was to observe the behavior, correctness, and functional robustness of the ASCON-128 RTL implementation when verified using NIST test vectors. While the current aim is a general implementation,  a synthesizable verified and ASIC-oriented hardware model is aimed to be developed which aligns with the lightweight cryptography standards set by NIST.Design:

Methods: ASCON-128 is an authenticated encryption algorithm which was developed in modular structured Verilog HDL that contained a permutation core, control unit, and state management logic which was complemented with functional verification using Cadence Xcelium along with NIST test vectors for verification of encryption, decryption, and generation of authentication tags.

Design: RTL implementation and verification study based on functional observation and simulation analysis.

Results: For the RTL simulation, the full functional correctness was verified and NIST reference ciphertexts and tags demonstrated exact matches. The design security integrity was validated due to the design robustness against altered inputs.

Conclusion: The RTL design in Verilog illustrates a secure and verified starting point for lightweight cryptography that is appropriate for ASIC implementation in IoT devices. This work paves the synthesis, power optimization and other more complex architectures that can be developed in future.

Key words: ASCON-128, Authenticated Encryption, IoT security, RTL design, Verilog

References

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